Method and apparatus for a programmable bitstream parser for audiovisual and generic decoding systems

ABSTRACT

A parser ( 100 ) for parsing a digital bitstream which includes both data information and programming information, where it is based on the programming information contained in the bitstream, is disclosed. The parser ( 100 ) included a buffer ( 110 ), a mode selector ( 200 ), a control circuit ( 300 ), and a data processor ( 400 ). The mode selector ( 200 ) determines whether one or more bits of the bitstream segment represent a mode selection code, and selects a parser mode in response to the mode selection code. The control circuit ( 300 ) receives and stores bits from the buffer when the bitstream parser ( 100 ) is in a program mode in order to reprogram the control circuit ( 300 ) with newly received program information, and uses the program information to generate one or more parsing signals when the bitstream parser ( 100 ) is in data mode. The data processor ( 400 ) received bits from the buffer ( 110 ) and parsing signals from the command circuit ( 300 ) when the bitstream parser is in the data mode, and parses the received bits in accordance with the parsing signals.

BACKGROUND OF THE INVENTION

I. Field of the Invention

The present invention relates to techniques for parsing a digitalbitstream, and more specifically, to programmable audiovisual andgeneric bitstream parsing techniques.

II. Description of the Related Art

In the digital environment, information is generally transmitted betweensystems in the form of coded bitstreams which represent audiovisual orother generic data. In order to be usable by the receiving system, notonly must such coded bitstreams must be decoded, but the bitstream mustbe parsed, i.e., separated into semantically meaningful units or“objects.”

For example, in the case of an MPEG-2 encoded bitstream, the bitstreammust be parsed into slices and macroblocks before the informationcontained in the bitstream is usable by an MPEG-2 decoder. The MPEG-2decoder uses the parsed bitstream to reconstruct the originalaudiovisual information.

In the past, the parsing operation has been performed bycustom-manufactured hardware and/or software. Such bitstream parserswould be programmed to separate an incoming bitstream based on somepreselected objective rules or criterion, such as the intrinsiccharacteristics of packets of information in the bitstream, ortransitions in characteristics between consecutive packets ofinformation. An example of such a parser is presented in U.S. Pat. No.5,414,650 issued May 9, 1995, to Hekhuis.

However, a significant problem with such a bitstream parser lies in thefact that the parsing rules are inflexible to changes in the syntax ofthe incoming bitstream. For this reason, there have been severalattempts to construct bitstream parsers which are in some sense“programmable” so that bitstreams with differing syntax can be acceptedby the same parser by reprogramming, rather than replacing, the parser.

For example, U.S. Pat. No. 5,371,547, issued Dec. 6, 1994, to Siracusaet al., discloses an apparatus for excising and reinserting invariableand variable data from an MPEG video data stream in order to reducetransmission bandwidth. The apparatus includes a parser which separatestransport header data and encoded MPEG payloads for presentation to anMPEG decoder in a suitable format. The parser, which examines eachtransport header to determine if the corresponding payload containsslice data, may be programmed to respond to the particular encodedprotocol.

European Patent Application No. 94107818, published Jul. 12, 1994, ofMatsushita Electric Industrial Co., Ltd. discloses an apparatus forre-compressing encoded video data into a more compact form that issuitable for recording on a digital storage medium. The apparatusincludes a variable length decoder (“VLD”) for parsing an inputbitstream and for extracting quantization parameters and/or quantizedcoefficients from other information. The VLD is implemented by way of aprogrammable digital signal processor (“DSP”), which may extractcoefficients or both parameters and coefficients.

While the above-mentioned techniques present bitstream parsers that areprogrammable by an external user, they fail to provide a fully flexibleparser because an external programmer must reprogram the parser everytime a new syntax is encountered by the parser. Accordingly, the priorart techniques do not provide for self-configuration of the parser basedon the syntax of the bitstream, but require external programming toadapt to changes in the bitstream syntax. Therefore, there exists a needin the art for a bitstream parsing technique which is fully adaptable tothe syntax used in the bitstream without the requirement of interruptingthe parsing operation to reprogram the bitstream parser every time a newsyntax is encountered.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a bitstream parsingtechnique which is programmable by the bitstream itself.

A further object of the present invention is to provide a parsingtechnique which is capable of redefining objects, recognizing certaincontext-sensitive objects, and recognizing certain repetitive objectsduring the parsing operation.

A still further object of the present invention is to provide anaudiovisual and generic bitstream parsing technique which isprogrammable by an incoming bitstream that contains programming softwareembedded into the audiovisual or generic data, so that the parsingprocess may be tailored depending on the specific application.

In order to meet these and other objects which will become apparent withreference to further disclosure set forth below, the present inventionprovides a parser for parsing a digital bitstream which includes bothdata information and programming information. The parser includes abuffer, a mode selector, a control circuit, and a data processor. Themode selector determines whether one or more bits of the bitstreamsegment represent a mode selection code, and selects a parser mode inresponse to the mode selection code. The control circuit receives andstores bits from the buffer when the bitstream parser is in a programmode in order to reprogram the control circuit with newly receivedprogram information, and uses the program information to generate one ormore parsing signals when the bitstream parser is in a data mode. Thedata processor receives bits from the buffer and parsing signals fromthe command circuit when the bitstream parser is in the data mode, andparses the received bits in accordance with the parsing signals.

In a preferred arrangement, the buffer is a shift buffer having aplurality of parallel outputs for bits of the bitstream segment which itstores, and the parser includes one or more buffer isolation gates toisolate each parallel output of the shift buffer and to provide one ormore non-isolated bits of the bitstream segment to the data processorand the control circuit.

In an especially preferred arrangement, the program mode selection anddata mode selection codes are simply start and end program codes,respectively. In such an embodiment, the mode selector advantageouslyincludes a first logic circuit which receives one or more bits of thebitstream segment from the buffer isolation gates, compares such bitswith one or more bits of the start and end program codes, and generatesa signal indicative of a program mode when a start code is determined orwhen a program mode signal was generated in an immediately previouscycle and an end code is not determined.

Such a mode selector also includes a second logic circuit generating await signal whenever the start or end program codes are determined bythe first logic circuit, and providing the wait signal to the bufferisolation gates so that any gate corresponding to a bit position of theshift buffer containing a bit corresponding to the start or end programcodes is disabled.

The control circuit may include a memory to receive and store programinformation for the bitstream parser and to receive and store the one ormore bits of new program information, and to reprogram the storedprogram information when the new program information is received by thecontrol circuit, as well as an instruction decoder circuit to retrieveprogram information from the memory and generating the one or moreparsing signals based on the retrieved program information.

In another preferred arrangement, the control circuit also includes aprogram counter to generate addresses of storage locations in the memoryto retrieve program information whenever the wait signal is notgenerated. The control circuit may generate a wait value signal, wherethe logic circuit is responsive to the wait value signal in generatingthe wait signal.

Advantageously, the instruction decoder can be connected to the modeselector to receive the mode signal, and to the buffer to receive newprogramming information, where one or more bits of the bitstream segmentrepresenting such programming information are stored in the memory onlywhen the instruction decoder receives the program mode signal.

The instruction decoder circuit may also beneficially be linked to thedata memory to retrieve previously processed data, where instructiondecoder generates one or more parsing signals based on both retrievedprogram information and attributes of the retrieved data.

The present invention also provides a method for parsing a digitalbitstream having both data information and programming information. Themethod requires receiving a segment of the digital bitstream insuccessive cycles; determining whether one or more bits of the receivedbitstream segment represents a mode selection code, where the modeselection code can be a data mode selection code or a program modeselection code; selecting a data mode when the data mode selection codeis determined and a program mode when the program mode selection code isdetermined; storing one or more bits of the bitstream portion as newprogramming information when the program mode is selected; generatingone or more parsing signals based on the stored programming informationwhen the data mode is selected; and parsing the received bitstream inaccordance with the generated parsing signals.

Preferably, the selecting step includes comparing the one or morereceived bits to the data and program mode selection codes, generating asignal indicative of a program mode when a program mode selection codeis determined, or when a program mode signal was generated in animmediately previous cycle and a data mode selection code is notdetermined, generating a wait signal whenever either mode selection codeis determined, and isolating one or more bits of the received bitstreamportion which correspond to either mode selection code.

When the programming information includes one or more commandinstructions and is stored in an addressable program memory, the parsingsignal generation step advantageously provides for determining addressesof a program memory where command instructions are stored, retrievingsuch command instructions from the stored programming information in theprogram memory, and generating the one or more parsing signals based onthe retrieved command instructions whenever a wait signal is notgenerated.

When parsed data is provided to a data memory, the method also providesfor the retrieving of preselected data from the data memory, determiningaddresses of the program memory where command instructions are stored,retrieving the command instructions from the stored program informationin the program memory, and generating one or more parsing signals basedon both the retrieved command instructions and the retrieved data.

The accompanying drawings, which are incorporated and constitute part ofthis disclosure, illustrate a preferred embodiment of the invention andserve to explain the principles of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a system diagram of a programmable bitstream parser inaccordance with the present invention;

FIG. 2 shows a parser mode selection circuit useful in the FIG. 1parser;

FIG. 3 shows a control circuit useful in the FIG. 1 parser;

FIG. 4 shows a data extraction unit useful in the FIG. 1 parser; and

FIG. 5 shows a instruction decoder useful in the FIG. 3 control circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, there is shown an exemplary embodiment of aprogrammable bitstream parser 100 in accordance with the presentinvention. The parser 100 is designed to read data from a bitstream,parse the data into semantically meaningful segments, and store theparsed data in appropriate memory positions in a data RAM 150. Thebitstream may include both data and programming information, and shouldbe delivered to the parser 100 in a serial fashion, i.e., one bit at atime at fixed time intervals.

The parser 100 includes shift buffer 110, buffer gates 120, parser modeselector 200, control 300, and data processor 400. The parser 100 issynchronous, and its components are controlled by a common system clock(not shown). Although the embodiment shown in FIG. 1 is designed toparse 64 bit wide segments of the incoming bitstream into 8 bit widewords for storage into data RAM 150, those skilled in the art willappreciate that with trivial modifications, parser 100 could be adaptedto handle bitstream segments of other widths, e.g. 128 bits, or to parsesuch bitstream segments into words of any length, e.g., 16, 32, or 64bits.

The size of the shift buffer 110, which may be a shift register, shouldbe chosen so that it is capable of storing the largest parsable entityof the bitstream syntax, which is a design parameter. In the embodimentshow in FIG. 1, the buffer can store a 64 bit wide segment from theincoming bitstream. Buffer 110 includes 64 parallel outputs 111, one foreach bit of the bitstream segment which is stores at any given time.

Each parallel output 111 of buffer 110 is connected to a bufferisolation gate 120. The isolation gates 120, whose operation will bedescribed in further detail below, are used to block or isolate certainbits stored in buffer 110 before the stored information is passed on todata processor 400 via data bus 121 or to control 300 via data bus 122.

At any given point in time, the parser can be in either a data (D) modeor a program (P) mode. In the D mode, the bitstream segment stored inbuffer 110 represents data. In this mode, the data is parsed by dataprocessor 400 into 8 bit words which are subsequently placed in memorylocations in RAM 150 via data bus 401. Control 300 provides addresslocations to RAM 150 via address bus 503, and enables writing to the RAM150 via read/write enable line 504.

In the P mode, at least a portion of the bitstream segment stored inbuffer 110 represents binary commands or instructions that indicate areconfiguration of the syntax for subsequent data in the bitstream. Inthis mode, the binary commands or instructions are loaded directly intocontrol 300 in order to reprogram the parser 100. The details of thisoperation are discussed below.

The parser mode selector 200 determines which mode the parser 100 shouldbe in. Referring to FIG. 2, a preferred arrangement of the mode selector200, buffer 110 and gate structure 120 are shown in greater detail.

In the embodiment show in FIG. 2, the D mode is a default mode, with theP mode being triggered by a special binary codeword (command code)included in the bitstream called P_START, and turned off with anotherspecial binary codeword called P_END. Exemplary values for all specialcommand codes can be found in the Appendix. At the start of each clockcycle, logical circuitry in mode selector 200 checks the bitstreamsegment stored in buffer 110 for the presence of these special commandcodes and switches the parser mode when necessary.

The current mode is stored as the first bit of control register 260(program flag, or PF). Control register 260 is an 8-bit register thatstores pertinent state information needed for the coordination of theparser's operations. At the start of a clock cycle, shift buffer 110reads 64 bits from the bitstream and shifts its contents to the right.The 64 stored bits B are compared to the P_START and P_END codewords incomparators 210 and 220, respectively, which each perform a logical ANDoperation. The outputs A1 and A2 of comparators 210 and 220,respectively, are fed to logic cell 230, which also received the PF flagfrom register 260 from line 261. Logic cell 230 performs the logicaloperation A1 OR PF NAND A2, to determine the new value of the flag PF.The PF flag is set to 1 when P_START is encountered, and is reset to 0when P_END is encountered; in all other cases it retains its previousvalue.

While the P_START or P_END codes are necessary in order to determinewhether the following bitstream segment represents data or programminginformation, the bits that represent the codes themselves are nototherwise useful to the parser, as they represent neither data norprogramming information. Accordingly, when a P_START or P_END codedetected, the bits which make up the code need to be isolated from theremainder of the parser. Bits that represent other codes which arediscussed below must similarly be recognized and isolated.

For this purpose, the mode selector 200 includes logic which generates ainput wait (IW) flag that is stored in control register 260. The outputsA1 and A2 of comparators 210 and 220, respectively, are fed to logiccell 240, which performs an OR operation, so that if either the P_STARTor P_END are present in the code, a signal indicative of the value ofthe P_START or P_END is placed on output line 241 logic cell 240. Inputstepping counter 250 receives the output of logic cell 240 to be setthereby.

In the case of other codes which need to be removed from the storedbitstream segment, a wait value (WV) signal from control 300 is sent tocounter 250 via line 501. In such case, the wait value signal sets thecounter to a numerical value equal to the number of bit positionsrequired by the code (from 1 to 64).

The input step counter 250 is 7-bits wide, to be able to handle up toand including 64 steps. The counter 250 counts the number of bits heldin buffer 110 that are to be isolated. When the counter contains anon-zero value, an IW flag is present in register 260, with theappropriate gate 120 receiving the IW flag via line 262. The ANDoperation performed by the buffer isolation gates 120 effectivelyisolate the appropriate buffer 110 positions which store bits thatrepresent the code.

When the counter 250 is set to a specific value, the parser 100 waitswhile an equal number of bits are inserted into the shift buffer fromthe input bitstream, while the isolated bits are shifted out. In thismanner, bits which correspond to codes are removed, and only bits thatrepresent data or programming information are passed through the gates120 and on to the data processor 400 or control 300.

In order to properly parse the input bitstream, control 300 must storeappropriate state information that will govern the sequence of stepsthat need to be taken by the data processor 400. The control 300 canstore information that controls the parsing of one or multiple parsableobjects. Where more than one type of parsable object is present in abitstream, the bitstream must include appropriate identificationinformation in order for the control to determine which stateinformation to use to parse the current object. Such information can beprovided by special object identification codewords that immediatelyprecede each object. The parser uses this information to determine which“program” to use for the current object.

As shown in FIG. 3, control 300 includes program RAM 310, instructiondecoder 500, program counter 320, additional counters 330 and 340, andmultiplexer 350. The command codes which control the operation of theparser are stored in program RAM 310, which in the embodiment shown inFIG. 3 can store codes as 8-bit words. When the parser is in the D mode,the control 300 sequences through the instructions stored in program RAM310 in order to parse the bitstream. The sequencing is performed by aprogram counter (PC) 320, which supplies addresses to RAM 310 by addressbus 506.

The PC 320 is reset by instruction decoder 500 whenever the modeselector 200 returns the parser to the D mode, and is advanced as eachinstruction is completed. The advance of the PC is suspended byinstruction decoder 500 when the input skip counter (SC) 250 isactivated, as indicated by IW flag via line 262. When multiple objectsare supported, reset occurs only when the downloaded program affectedthe object currently being parsed by data processor 400, if any. Thisallows downloading of code while another object is being parsed.

The retrieved instruction is fed to the instruction decoder 500 viaprogram RAM data bus 505. The instruction decoder 500 determines how thenext segment of data will be parsed, and how many input bits whichrepresent object identification codewords should be discarded, i.e., thevalue loaded to the skip counter SC 501. The instruction decoder will bedescribed in further detail below.

When an instruction requires than 1 word, instruction decoder 500increments the PC 320 to obtain more data from program RAM 310 asappropriate. A program instruction is terminated by the code END; the PC320 is then reset to its original value so that parsing of the nextobject can commence.

When the mode selector 200 determines that the parser in the P mode, asindicated by the PF flag on line 261, the programming informationcontained in the incoming bitstream is utilized by control 300 asfollows. The P_START code recognized by the mode selector 200 isfollowed by an address in program RAM 310 where the programminginformation should be stored. The address and programming information isreceived by control 300 via data bus 122 in exactly the same way as itshould be stored in the program memory, which is controlled by thecreator of the program prior to its insertion in the bitstream fordownloading. Hence the control 100 only needs to transfer all bytessucceeding the P_START code (and the start address) to the specifiedprogram RAM address, stopping when it encounters the P_END code.

If the system only supports single object parsing, after the P_END codeis encountered the PC is reset to the address where the program wasloaded. If multiple object parsing is supported, then the reset occursonly if the downloaded code affected the object currently being parsed,if an object is being parsed by data processor 400.

Referring to FIG. 4, data processor 400 includes a masking and signextension unit 410 (MSU), and a multiplexer 420. The MSU 410 receivesthe 64-bit wide bitstream segment from buffer 110 via data bus 121. MSU410 also receives 8 bits of command information, a sign extension signal571, and an enabling signal 572 from the instruction decoder 500 via bus502.

The command information, which is stored in a Register A 510 of theinstruction decoder 500, determines how may bits from the bitstreamsegment should be considered by the MSU 410; the remaining bits arediscarded. The five high order bits stored in Register 510 indicate thelength of the parsed field, in bytes, minus 1, which is the result of aninteger division by 8. In the embodiment shown in FIG. 4, only the bitsin positions 3-5 of register 510 are required for this purpose, sincethe largest parsable entity is 64 bits wide. Thus, only the registeroutputs from bit positions 3-5 are connected to MUX 420, so that fromone to eight bytes of data may be transferred to data RAM 150 via databus 401.

Therefore, when the MSU is enabled via line 571, it sign extends thebits which it is directed to use via the signal on line 572, andtransfers single or multiple byte long objects to the data RAM 150 byway of the 8:1 MUX 420. This data is stored in data RAM 150 at addresseswhich are determined by the instruction decoder, as explained below.

Referring now to FIG. 5, the instruction decoder 500 is explained ingreater detail. The instruction decoder includes a set of registers 510,520, 530, 540, 550, and 560, associated MUXs 511, 521, 555 and 565, asequencer 570, and an arithmetic and logic unit 580. The instructiondecoder 500 is the coordinating circuit for the parser 100.

Sequencer 570 is a state machine that enables control signals atappropriate intervals according to the inputs which it receives. Asshown in FIG. 5, the sequencer receives the above-discussed IW and PFflags from the mode selector 200 via lines 261 and 262, as well asprogramming information from the program RAM 310 via program RAM databus 505, and new programming information from data bus 122 via MUX 521,register C 520, and output line 525. In addition to providing enablingand sign extension signals to data processor 400 and the wait valuesignal to mode selector 200, the sequencer also provides a read/writeenable signal to the external data RAM 150 via line 504, and controlsthe overall operation of the instruction decoder 500 by way of commandlines (not shown) to each component listed above, as well as to MUX 350and counters 320, 330 and 340 shown in FIG. 3.

Referring again to FIG. 3, when the parser is placed in the programmode, as indicated by the presence of the PF signal on line 261, the twobytes of information which immediately follow the P_START code arerouted to the program counter 320 by data bus 122 and MUX 350. The valuewhich the program counter held in the immediately previous cycle, which,as further discussed below, remains important when parsing fields areindirectly represented, is simultaneously routed to a second programcounter 330. The value stored in the program counter 320 represents thebeginning address in program RAM 310 where new programming informationis to be stored.

Subsequent bytes of information are not routed to the program counter320, but instead are routed to register C 520 via MUX 521. The firstbyte of information routed to register C is loaded into program RAM 310via bus 505 at the address stored in program counter 320. As additionalbytes of information are routed to register C, the program counter 330is incremented by a control signal from the sequencer (not shown), andthe additional bytes of information are likewise stored in program RAM310 at such incremented address locations. When the P_END code isencountered, the PF signal goes to 0, and the sequencer 570 resets theprogram counter 320. Normal data mode operations resume.

In the data mode, programming information stored in the program RAM 310are loaded into register C 520, with the number of bits of the currentbitstream segment to be parsed is stored in register a 510. Registers D1and D2 530, 540, are used to obtain addresses from the program RAM 310that are used in the case of indirect parsing representations. RegistersE1 and E2, 550, 560, are used to supply address values to the externaldata RAM 150 via address bus 503, so that parsed data can be stored inthe data RAM 150 at an appropriate location.

With control 300, the parser 100 can parse several different types ofdata syntax, including constant-length direct representation bit fieldsor “Fixed Length Codes” (FLCs), which include the encoded value as it isto be used by the decoder/receiver, variable length directrepresentation bit fields or “variable length FLCs,” which are FLC forwhich the length is determined by the context of the bitstream (i.e.,another field that has previously appeared), constant-length indirectrepresentation bit fields, which require an extra lookup into anappropriate table, and variable-length indirect representation bitfields, i.e., traditional Huffman codes. The operation of control 300 inthe data mode will now be described in the context of these varying datasyntaxes.

EXAMPLE 1 Fixed-Length Codes

This is the simplest bit field, and is described by a command code whichidentifies the type of data to be parsed followed by one byte thatindicates the number of bits used in the representation. An example is a3-bit integer. Table 1 depicts the command format, were PC indicates thestarting address loaded into program counter 320.

TABLE 1 Position Content Description PC CODE Data type PC+1 lengthLength in bitstream

With reference to Table 1, when the parser 100 receives an objectidentification code which identifies the byte of data stored in programRAM 310 at the address PC, the command stored in RAM 310 at address PCis loaded into register C, informing the sequencer that a fixed-lengthcode is to be parsed. The sequencer 570 increments the program counter320 by 1, thereby permitting the program counter to read the address inprogram RAM 310 which holds the length value for the correspondingobject in the bitstream. This value is placed in register A via theprogram RAM's data bus 505 and MUX 511, and used by data processor 400to properly parse the current bitstream segment, as discussed 15 above.

Table 2 indicates various codes may be used to signify various types offixed-length codes. In Table 2, “expanded size” indicates the size ofthe parsed quantity after it is parsed.

TABLE 2 Expanded Type Code Size int INT_D 32  unsigned int UINT_D 32 char CHAR_D 8 unsigned char UCHAR_D 8

EXAMPLE 2 Variable-Length FLC's

Variable-length direct representation bit fields are similar to theconstant-length ones, with a difference being that the size of the bitfield is determined by a variable in the external data RAM 150, ratherthan in the program RAM 310. This allows an already parsed field todetermine the length of a future field. An example is an integer whoselength is determined by a field that has previously been parsed. Table 3shows the command format of such codes.

TABLE 3 Position Content Description PC CODE Data type PC+1 addr0 Firstbyte of address of value in data RAM that determines length PC+2 addr1Second byte of address of value in data RAM that determines length

With reference to Table 3, when the parser 100 receives an objectidentification code which identifies the byte of data stored in programRAM 310 at the address PC, the command stored in RAM 310 at address PCis loaded into register C, informing the sequencer in this case that avariable-length FLC is to be parsed. In such a case, the sequencer 570initiates two additional read cycles from the program RAM 310 in orderto read the addr0 and addr1 bytes, which are temporarily stored inregisters D1 and D2 530, 540. The sequencer 570 then uses the valuesstored in registers D1 and D2 to address the external data RAM 150 vialines 535, 545, MUX's 555 and 565, and address bus 503. Data at theindicated program RAM 150 addresses is retrieved via program RAM databus 401, fed through MUX 511, and stored in Register A 510 to inform thedata processor 400 of the appropriate number of bits to parse.

Table 4 indicates the various codes may be used to signify various typesof variable-length FLC's.

TABLE 4 Expanded Type Code Size int INT_I 32  unsigned int UINT_I 32 char CHAR_I 8 unsigned char UCHAR_I 8

EXAMPLE 3 Constant-Length Indirect Representation Bit Fields

Indirect representation bit fields require the use of a table that mapsthe parsed input value to a set of actual values for the parsedparameter. When the parsed input has fixed length it is aconstant-length indirect representation, while a parsed input havingvariable length is variable-length or Huffman code. Such parsing tablesare stored in a separate area of the program RAM 310. As shown in Table5, a parsing table has one index column and one or more output columns(hence it defines a one-to-many mapping), where each output column mayhave its own data type.

TABLE 5 Index Value 1 (int) Value 2 (char) 0  42  4 1 −58 −1

When the parser is in the program mode, a map may stored in the programRAM 310 in the following manner. First, the length of the index column(in bits) is stored in the first byte, the number of value columns isstored in the second byte, and the number of bytes to skip to get at theindex of the first row is stored in the third byte. The data type ofeach value is then stored in subsequent bytes using abstract, direct, orindirect representation codes. Finally, the actual data is stored, onerow at a time, including the index value; each value (except the index)is preceded by an “escape” byte, while the index is immediately followedby the number of bytes to skip in order to go to the representation ofthe next row (in order to facilitate quick jumps to subsequent rowswithout parsing the current one).

Abstract representation codes are special codes that just indicate thetype of data as stored in the map (CHAR, UCHAR, INT, UINT). The use ofan escape byte allows the insertion of direct and indirectrepresentations that substitute actual values, to thereby permit anextra degree of sophistication in the map: the map's functionality canbe extended to include “escape” codes that trigger parsing of furtherdata from the bitstream in order to obtain the value of the mapping. Anexample of table mapping with an escape code is shown in Table 6.

TABLE 6 Index Value 1 (int) Value 2 (char) 00 42  4 01 INT_D, 3 −1

The map indicated in Table 6 is stored in program RAM 310 as indicatedin Table 7, where integer values require four bytes and word valuesrequire one byte.

TABLE 7 Address 0 1 2 3 4 5 6 7 A 1 2 2 INT CHAR 0 7 0 A+8 0 0 0 42 0 41 8 A+16 1 INT_D 3 0 −1

Thus, referring to the five top left entries in Table 7, the mapindicated in Table 6 has an index that is one bit long (index values 0and 1), has two value columns, requires two bytes to be skipped to gotothe index of the first row and has INT and CHAR data types. Proceedingfrom the sixth entry in Table 7, the first index is 0, the row skipvalue is seven, the first escape byte is 0, the first data entry is 0,0, 0, 42 (integer), the second escape value is 0, the second data entryis 4 (character), the second index value is 1, and so on.

As illustrated, each data value is preceded by its escape flag; the flagis set to one only before the element in position A+17, to trigger theescape to INT_D, 3. Accordingly, if the value 1 is encountered in thebitstream, then in order to obtain the value for the first column entrythe parser will need to parse 3 subsequent bits from the bitstream. Suchrepresentation avoids the need to specify an INT_I plus the address, toindicate a variable length constant representation entry. Note that theescape types must be of the same type as the column they appear in.

The map type object identification code is indicated by a special code(MAP) stored in the program RAM 310, followed by the address where themap's description is stored. The command format for such codes aredepicted in Table 8.

TABLE 8 Position Content Description PC MAP Map code PC+1 addr0 Firstbyte of address of map's definition in data RAM PC+2 addr1 Second byteof address of map's definition in data RAM

With reference to Table 8, when the parser 100 receives an objectidentification code which identifies the byte of data stored in programRAM 310 at the address PC, the command stored in RAM 310 at address PCis loaded into register C, informing the sequencer that a MAP type dataformat is to be parsed. In such a case, the sequencer 570 initiates twoadditional read cycles from the program RAM 310 in order to read theadd0 and addr1 bytes, which are temporarily stored in registers D1 andD2 530, 540. The value in program counter 320 is shifted to counter 330,and the value in the registers D1 and D2 is shifted to the programcounter 320.

The next memory addresses, i.e., the length of the index, the number ofvalue columns, and the number of bytes to skip are retrieved and storedin register C 520, sequencer 570, and register A 510, respectively. Atthis point, the program counter 320 indicates the address of the firstdata type; this value is stored in the extra counter 340 for possibleuse if a match is found. The number of bytes to skip, stored in registerA 510, is added to the value held in the program counter 320 to indicatethe address of the first index, which is loaded into Register A andcompared by ALU 580 with the input. If there is no match, the nextprogram data byte is read in order to jump to the next index.

Where there is a match, the sequencer 570 increments the program counter320 by one, to bypass the skip byte address, and sends a wait value flagvia line 501 to the mode selector 200 so that the shift buffer 110 isshifted by the number of bits indicated in register C. The new addressindicated by program counter 320 corresponds to the escape flag, whichis loaded into register C 520. If the value loaded into register C isnon-zero, the command that immediately follows is executed, and there isno need to use the value previously stored in the counter 340.

If, however, the value of the escape flag is zero (e.g., a non-escapedvalue), the sequencer exchanges the values stored in counters 320 and340, thereby placing the address of the data type previously stored incounter 340 into counter 320 in order to retrieve the data type from theprogram RAM 310. This value is stored in register C 520. The valuesstored in counters 320 and 340 are then again swapped, to return thevalue held by program counter 320 to indicate a data address. The dataat this address is retreived from program RAM 310 and placed intoregister A.

After parsing of the field is completed, the values stored in registers320 and 340 are again exchanged, and the sequencer proceeds to locatethe instruction for the second field. This process is continued untilall MAP columns entries are exhausted.

EXAMPLE 4 Variable-Length Indirect Representation Bit Fields

Variable length indirect representation bit fields differ from theirconstant-length counterparts in that the length of the index column isnot fixed. For example, the map show in Table 6 could be modified asshown in Table 9:

TABLE 9 Index Value 1 (int) Value 2 (char) 0b0 42  4 0b10 INT_D, 3 −1

The notation ‘0b’ is used to denote a binary number (similar to ‘0x’ forhexadecimal). As shown in Table 9, the index values have differentlengths (1 and 2). This is a very common situation in actual audio andvideo encoders, and allows for a reduction of the average number of bitsnecessary to represent a given quantity if the values are notequiprobable, so that more probable values are assigned shorter indices.

The map format described above can be used to store such information inthe program RAM 310; modifications are necessary, however, in order toaccount for the varying index size. More specifically, the storage ofthe table is modified by storing the number of value columns is in thefirst byte, and the number of bytes to skip to get at the index of thefirst row in the third byte, with the data type of each value beingstored in subsequent bytes using abstract, direct, or indirectrepresentation codes. Finally, the actual data is stored, one row at atime, including the index value preceded by its length. Each value,except the index, is preceded by an escape byte. The index is followedby the number of bytes to skip to go to the representation of the nextrow, thus permitting quick jumps between rows without additionalparsing.

For example, the map of Table 9 would have an in-memory representationas illustrated in Table 10.

TABLE 10 Address 0 1 2 3 4 5 6 7 A 2 2 INT CHAR 1 0 4 0 A+8 0 0 0 42 0 42 1 A+16 5 1 INT_D 3 0 −1

The command code used to trigger variable-length indirect representationbit fields is VMAP, which is followed by the address of the programdescription in the program RAM. Table 11 shows the format ofvariable-length indirect representation bit fields.

TABLE 11 Position Content Description PC VMAP Variable length map codePC+1 addr0 First byte of address of map's definition in data RAM PC+2addr1 Second byte of address of map's definition in data RAM

The parsing operations are identical to those described in Example 4above, with the only difference lying in the fact that the index lengthis not obtained from the map's header, but directly from the bytepreceding the index.

EXAMPLE 5 General Arithmetic and Flow Control

In many practical coding situation, the bitstream syntax may becontrolled-by context, with the presence of a field being determined bythe value of an already parsed parameter. Similarly, the number offields present may be controlled by some parameter. This dependence mayalso not be direct, in the sense that the actual value may be anexpression involving bitstream parameters and not the value of anyspecific parameter. For these reasons, the instruction decoder includesa general purpose arithmetic and logic unit (ALU) 580. The commandslisted in Table 12 are supported by ALU 580.

TABLE 12 Command Operation Description LOAD addr A←RAM [addr] Load fromdata memory location STO addr RAM [addr]←A Store to data memory locationADD addr A←A+RAM [addr] Add memory location to accumulator SUB addrA←A−RAM [addr] Subtract memory location from accumulator JNZ addr if A≠0then PC←addr Jump to memory location if accumulator is not 0

With reference to Table 12, ‘A’ indicates the ALU's accumulator, i.e.,register A 510, RAM[x] denotes the contents of external data RAM 150 ataddress ‘x’, and ‘addr’ is a two byte entity that addresses the data RAMvia registers D1 and D2 530, 540.

As illustrated in the foregoing examples, the instruction decoder 500can implement all different types of for and while loops, as well asgeneral expression evaluation. The ALU 580 can be any off-the shelf unitwhich uses 2's complement arithmetic, and does not require a stack, astack pointer or a “return” instruction.

Although the principals described in the foregoing specification aregenerally applicable to current image and video compression techniquessuch as JPEG, H.261, MPEG-1, MPEG-2, H.263, which require a particularbitstream sytax, the present invention has particular applicability toobject-based compression techniques such as the MPEG-4 standardizationeffort by the ISO/IEC JTC1/SC29/WG11 group, which permits a variablebitstream sytax, as well as to any generic digital bitstream which has avarying syntactic configuration.

In the context of the proposed MPEG-4 standard and its associated MSDL-Slanguage, the present invention provides both for programmability of theparser as well as for the separation of the bitstream parsing processfrom bitstream processing. As described herein, the parser can beprogrammed by the incoming bitstream in three general ways. First, theparser can be programmed to recognize certain high-level objectidentifiers (e.g., slices or tools, which may be tagged to the bitstreamduring encoding) and to redefine such objects during parsing. Second,the parser can be programmed to recognize certain context-sensitiveobjects, i.e., objects that require the presence of other objects to berecognizable (an “if then else” object description). Third, the parsercan be programmed to recognize certain repetitive objects and to applythe same syntax to parse the repetitive bitstream until some conditionis met (a “for while do” object description). Accordingly, those skilledin the art will appreciate that the foregoing description presents abitstream parsing technique that is fully adaptable to the syntax usedin a digital bitstream without the requirement of interrupting theparsing operation to reprogram the bitstream parser every time a newsyntax is encountered.

Although an exemplary embodiment was described herein, variousmodifications and alterations to the described embodiment will beapparent to those skilled in the art in view of the teachings herein.For example, while the parser 100 is designed to accept a serialbitstream, parallel input can also be accommodated, e.g., when theinformation is provided one byte at a time, simply by adding aparallel-to-serial converter using a shift buffer with parallel loading.In addition, while the mode selector described above is designed tocompare the incoming bitstream to a P_START code and a P_END code, thelogic of the mode selector 200 could be easily modified to handle otherbitstream codes which may indicate the arrival of programming or datainformation. Likewise, while the described embodiment uses a specialprogram RAM 310 to store command information, it is also possible to usethe external data RAM 150 for the same purpose.

It will thus be appreciated that those skilled in the art will be ableto devise numerous systems and methods which, although not explicitlyshown or described herein, embody the principles of the invention andare thus within the spirit and scope of the invention.

Appendix Codeword Value Symbol (Hex) Description P_START 00 00 Enterprogram mode (exiting data 00 00 mode); following bytes indicate place00 00 in program RAM where program should 00 01 be stored P_END 00 00Exit program mode (entering data 00 00 mode) 00 00 00 02 NOP 00 Nooperation (ignored) INT 01 Integer value, 32 bits UINT 81 Unsignedinteger value, 32 bits CHAR 02 Character value, 8 bits UCHAR 82 Unsignedcharacter value, 8 bits INT_D 11 Parse data of given length to a 32- bitinteger; length follows in next byte and sign extension is performed asneeded UINT_D 91 Parse data of given length to a 32- bit unsignedinteger; length follows in next byte CHAR_D 12 Parse data of givenlength to an 8- bit integer; length follows in next byte and signextension is performed as needed UCHAR_D 92 Parse data of given lengthto an 8- bit unsigned integer; length's address in data RAM follows innext two bytes INT_I 17 Parse data of given length to a 32- bit integer;length's address in data RAM follows in next two bytes and signextension is performed as needed UINT_I 97 Parse data of given length toa 32- bit unsigned integer; length's address in data RAM follows in nexttwo bytes CHAR_I 18 Parse data of given length to an 8- bit integer;length's address in data RAM follows in next two bytes and signextension is performed as needed UCHAR_I 98 Parse data of given lengthto an 8- bit unsigned integer; length's address in data RAM follows innext two bytes MAP F0 Fixed-length mapped data; address of mapdefinition in program RAM is indicated in the following two bytes. VMAPF1 Variable-length mapped data; address of map definition in program RAMis indicated in the following two bytes. LOAD 10 Load accumulator withvalue from data memory; address follows in next two bytes STO 20 Storeaccumulator in data memory; address follows in next two bytes ADD 30 Adddata memory value to accumulator; address follows in next two bytes SUB40 Subtract data memory value from accumulator; address follows in nexttwo bytes JNZ 50 Jump to specified address if accumulator has non-zerovalue; address follows in next two bytes END FF End of object parsingprogram

What is claimed is:
 1. A programmable bitstream parser for parsing adigital bitstream having both data information and programminginformation, and for providing parsed data to a data memory, comprising:(a) a buffer for receiving and temporarily storing a segment of saiddigital bitstream; (b) a mode selector, coupled to said buffer todetermine whether one or more bits of said bitstream segment represent amode selection code, and selecting a parser mode in response to saidmode selection code to place said bitstream parser in a data mode whensaid mode selection code is a data mode selection code and in a programmode when said mode selection code is a program mode selection code; (c)a control circuit, coupled to said buffer to receive and store one ormore bits of said bitstream segment from said buffer when said bitstreamparser is in said program mode and reprogramming said control circuitwith newly received program information, and using said programinformation to generate one or more parsing signals when said bitstreamparser is in said data mode; and (d) a data processor, coupled to saidbuffer and to said control circuit to receive one or more bits of saidbitstream segment from said buffer and said parsing signals from saidcontrol circuit when said bitstream parser is in said data mode, parsesaid received bits in accordance with said parsing signals, and providesaid parsed data to said data memory.
 2. The apparatus of claim 1,wherein said buffer is a shift buffer having a plurality of paralleloutputs for bits of said bitstream segment stored therein.
 3. Theapparatus of claim 2, wherein said shift buffer is a buffer having asize sufficient to store a number of bits required by a largest parsableentity of any syntax handled by said bitstream parser.
 4. The apparatusof claim 2, further comprising one or more buffer isolation gates, eachcoupled to a respective one of said parallel outputs of said shiftbuffer, and to said mode selector, said data processor and said controlcircuit, said buffer gates receiving and isolating said parallel outputsof said shift buffer and providing one or more non-isolated bits of saidbitstream segment to said data processor and said control circuit. 5.The apparatus of claim 4, wherein said program mode selection code is astart program code and said data mode selection code is a end programcode, and wherein said mode selector includes a first logic circuitreceiving one or more bits of said bitstream segment from said bufferisolation gates, said first logic circuit comparing said one or morebits of said bitstream segment with one or more bits of said startprogram code and with one or more bits of said end program code togenerate a signal indicative of a program mode when a start code isdetermined from said comparing or when a program mode signal wasgenerated in an immediately previous cycle and an end code is notdetermined from said comparing.
 6. The apparatus of claim 5, furthercomprising a second logic circuit, coupled to said first logic circuitand to said buffer isolation gates, said second logic circuit generatinga wait signal whenever said start program code or said end program codeis determined by said first logic circuit, and providing said waitsignal to said buffer isolation gates so that any gate corresponding toa bit position of said shift buffer containing a bit corresponding tosaid start program code or said end program code is disabled, therebyisolating said corresponding bit.
 7. The apparatus of claim 1, whereinsaid control circuit comprises: (i) a memory, coupled to said buffer toreceive and store program information for said bitstream parser and toreceive and store said one or more bits of new program information, andto reprogram said stored program information when said new programinformation is received by said control circuit; and (ii) an instructiondecoder circuit, coupled to said memory and to said data processor toretrieve program information from said memory and generating said one ormore parsing signals based on said retrieved program information.
 8. Theapparatus of claim 7, wherein said mode selector further comprises alogic circuit for generating a wait signal whenever a mode selectioncode is determined, and wherein said control circuit further comprises aprogram counter coupled to said logic circuit and to said memory togenerate addresses of storage locations in said memory to retrieveprogram information therefrom whenever said wait signal is notgenerated.
 9. The apparatus of claim 8, wherein said control circuit iscoupled to said logic circuit and generates a wait value signal, saidlogic circuit being responsive to said wait value signal in generatingsaid wait signal.
 10. The apparatus of claim 7, wherein said modeselector generates a mode signal representative of a mode selectedthereby, and wherein said instruction decoder is coupled to said modeselector to receive said mode signal therefrom.
 11. The apparatus ofclaim 10, wherein said instruction decoder is coupled to said buffer andwherein said one or more bits of said bitstream segment are stored insaid memory only when said instruction decoder receives said programmode signal.
 12. The apparatus of claim 7, wherein said instructiondecoder circuit is coupled to said data memory to retrieve datatherefrom and said instruction decoder generating said one or moreparsing signals based on said retrieved program information andattributes of said retrieved data.
 13. A programmable bitstream parserfor parsing a digital bitstream having both data information andprogramming information, comprising: (a) temporary storage means forreceiving and temporarily storing a segment of said digital bitstream,said temporary storage means having a plurality of parallel outputscorresponding to respective bit positions thereof; (b) mode selectionmeans coupled to said temporary storage means for determining whetherone or more bits of said bitstream portion represent a mode selectioncode and for selecting a parser mode in response to said mode selectioncode, said bitstream parser being placed in a data mode when a data modeselection code is determined and in a program mode when a program modeselection code is determined; (c) control means, including programmemory means storing programming information therein, coupled to saidtemporary storage means for receiving and storing one or more bits ofsaid bitstream segment in said program memory means when said bitstreamparser is in said program mode and further including means forreprogramming said program with newly received programming informationand means for generating one or more parsing signals in response to saidstored programming information when said bitstream parser is in saiddata mode; and (d) data extraction means, coupled to said temporarystorage means and to said control means, for receiving one or more bitsof said bitstream segment from said temporary storage means and saidparsing signals from said command means when said bitstream parser is insaid data mode and including means for parsing said received bits inaccordance with said parsing signals.
 14. The apparatus of claim 13,wherein said temporary storage means includes means for isolating eachof said parallel outputs of said temporary storage means, and means forproviding one or more non-isolated bits of said bitstream segment tosaid data extraction means and said control means, and wherein said modeselection means further comprises: (i) first logic means having meansfor receiving said one or more non-isolated bits, means for comparingsaid one or more bits with said data mode selection code with saidprogram mode selection code, and means for generating a signalindicative of a program mode when a program mode selection code isdetermined by said comparing means or when a program mode signal wasgenerated in an immediately previous cycle and a data mode selectioncode is not determined by said comparing means; and (ii) second logicmeans, coupled to said first logic means, for generating a wait signalwhenever said data mode selection code or said program mode selectioncode is determined by said first logic means, and having means forproviding said wait signal to said isolation means so that any of saidparallel outputs corresponding to a bit position in said temporarystorage means which contains a bit of said data mode selection code or abit of said program mode selection code is isolated.
 15. The apparatusof claim 14, wherein said control means further comprises instructiondecoding means, coupled to said program memory means, to said dataextraction means and to said second logic means, for retrievingprogramming information from said program memory means, and having meansfor generating said one or more parsing signals based on said retrievedprogramming information whenever said wait signal is not generated. 16.A method for parsing a digital bitstream having both data informationand programming information comprising the steps of: (a) receiving asegment of said digital bitstream in successive cycles; (b) determiningwhether one or more bits of said received bitstream segment represents amode selection code, said mode selection code comprising a data modeselection code or a program mode selection code; (c) selecting a datamode when said data mode selection code is determined and a program modewhen said program mode selection code is determined; (d) storing one ormore bits of said bitstream portion as new programming information whensaid program mode is selected; (e) generating one or more parsingsignals based on said stored programming information when said data modeis selected; and (f) parsing said received bitstream in accordance withsaid generated parsing signals.
 17. The method of claim 16, wherein step(c) further comprises the step of isolating one or more bits of saidreceived bitstream segment corresponding to said data mode selectioncode or to said program mode selection code.
 18. The method of claim 16,wherein step (c) further comprises the steps of: (i) comparing said oneor more bits of said received bitstream segment to said data modeselection code and to said program mode selection code; and (ii)generating a signal indicative of a program mode when a program modeselection code is determined or when a program mode signal was generatedin an immediately previous cycle and a data mode selection code is notdetermined.
 19. The method of claim 18, wherein step (c) furthercomprises the steps of: (iii) generating a wait signal whenever saiddata mode selection code or said program mode selection code isdetermined; and (iv) isolating, in response to said wait signal, one ormore bits of said received bitstream portion which correspond to saiddata mode selection code or to said program mode selection code.
 20. Themethod of claim 19, wherein step (d) further comprises the step ofreprogramming said stored programming information when said newprogramming information is received.
 21. The method of claim 20, whereinsaid programming information comprises one or more command instructionsand is stored in an addressable program memory and step (e) furthercomprises the steps of: (i) determining addresses of said program memorywhere command instructions are stored; (ii) retrieving said commandinstructions from said stored programming information in said programmemory; and (iii) generating said one or more parsing signals based onsaid retrieved command instructions whenever said wait signal is notgenerated.
 22. The method of claim 19, further comprising the step ofgenerating a wait value signal determinative of the number of bits ofsaid received bitstream segment to be isolated, said isolating stepbeing responsive to said wait signal and to said wait value signal. 23.The method of claim 16, further comprising the step of providing saidparsed data to a data memory.
 24. The method of claim 23, wherein step(e) further comprises: (i) retrieving preselected data from said datamemory; (ii) determining addresses of said program memory where commandinstructions are stored; (iii) retrieving said command instructions fromsaid stored program information in said program memory; and (iv)generating said one or more parsing signals based on said retrievedcommand instructions and said retrieved data.